1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to an on-die termination circuit for a semiconductor integrated circuit device.
2. Description of the Related Art
Lines used to transmit signals among different integrated circuit (IC) devices (e.g., microprocessor, memory controller, memory, etc) are often terminated by a termination circuit to prevent signals from being reflected.
Signal reflection degrades signal integrity, and particularly as at higher system operating speeds, signal reflection can have a significant effect on signal integrity. In general, in order to prevent the maximum amount of signal reflection, a termination circuit is installed on a signal line close to an IC device.
Generally, a termination circuit includes a termination resistor and a termination voltage. The circuit is generally positioned on a board at the end of a signal line which transmits signals between IC devices. However, when there are a large number of signal lines on a board, it can be hard to position the termination circuit on the board. A technique has been developed that does not terminate signals on the board. Instead the signals are terminated in the IC circuit which is mounted on the board. The technique is called an on-die termination technique.
FIG. 1 shows a circuit diagram of a conventional on-die termination circuit. The on-die termination circuit shown in FIG. 1 includes a PMOS transistor P, an NMOS transistor N, an inverter I, a first termination resistor R1, and a second termination resistor R2. In FIG. 1, “ODT_EN” denotes a control signal that is on-die terminated. Pad 10 represents an input pad in the IC device, and “VDDQ” represents a power voltage.
The on-die termination circuit of FIG. 1 operates as follows: When the on-die termination control signal ODT_EN has a low level signal applied, the inverter I outputs a signal with a high level. Therefore, a signal that has a low level is applied to a gate of the NMOS transistor N and a signal that has a high level is applied to a gate of the PMOS transistor P, so that both the NMOS transistor N and the PMOS transistor P are turned off. In this state the on-die termination circuit does not operate.
When the on-die termination control signal ODT_EN has a high level signal applied, the inverter I outputs a signal that has a low level. Therefore, a signal that has a high level is applied to a gate of the NMOS transistor N, and a signal that has a low level is applied to a gate of the PMOS transistor P. In this state both the NMOS transistor N and the PMOS transistor P are turned on, and a signal applied to the pad 10 is terminated to a predetermined termination voltage level. The termination voltage level has a value between a power voltage VDDQ and a ground voltage. If the first termination resistor R1 and the second termination resistor R2 have the same resistance value, the magnitude of the terminating voltage is the magnitude of the power voltage divided by two.
In other words, the on-die termination circuit of FIG. 1 obtains a desired resistance value using the two termination resistors R1 and R2 which are connected in parallel. The NMOS transistor N and the PMOS transistor P are used to obtain a resistance value that is smaller than resistance values of either of the termination resistors R1 and R2. A high value signal ODT_EN operates the on-die termination circuit to terminate the signal with a predetermined termination voltage. When a low value ODT_EN signal is applied, the on-die termination circuit does not operate.
The size of the transistors can be increased to reduce the resistance value of the transistors. However, when the size of a transistor is increased, the capacitance of the transistor is also increased. When the capacitance of the transistor increases, the input capacitance of the on-die termination circuit also increases. Furthermore, the PMOS transistor should have 2.5 to 3 times the width of the NMOS transistor in order to have the same resistance value as the NMOS transistor, and thus, the capacitance of the PMOS transistor is similarly increased. Accordingly, the on-die termination circuit of FIG. 1 has disadvantages associated with the capacitance of the PMOS transistor.
In addition, the electrical characteristics of the NMOS transistor and PMOS transistor may be different due to differences in the manufacturing process. If the electrical characteristics of the NMOS transistor and the PMOS transistor are different, a signal applied through the pad 10 may be distorted.